Conventional SRAM systems store binary information in cells comprising a pair of cross coupled inverters. Typically, these systems are "single port" and provide one path for reading information from the cell and for writing information into the cell. Multiport SRAMs are also available which allow completely independent and asynchronous access to each memory cell from a pair of ports (i.e., a dual-port memory). In FIG. 1, a block diagram is shown of a dual port SRAM 10 which has independent read/write circuits 12 and 14. Read/write circuit 12 has access to SRAM 10 through port A whereas read/write circuit 14 has access through port B. Both read/write circuits operate independently and asynchronously and can either write or read into any cell within SRAM 10. Microprocessors 16 and 18 access SRAM 10 through read/write circuits 12 and 14 respectively.
In FIG. 2, a conventional CMOS dual port SRAM cell is shown which consists of 4 memory transistors 20, 22, 24 and 26 and 4 access transistors 28, 30, 32 and 34. Most of the transistors in the circuit of FIG. 2 are n-channel MOS devices, except for transistors 20 and 22 which are p-channel MOS devices. "A port" bit lines 36 and 38 (BL-AT.BL-AC) provide true and complement access to and from the memory cell. Bit lines 40 and 42 (BL-BT, BL-BC)provide true and complement access to the cell port B. Word lines 44 and 46 (WL-A, WL-B) provide word line access from ports A and B respectively. V.sub.DD and GND designate supply and common potentials.
The conventional technique for reading or writing in the cell of FIG. 2 involves the differential sensing of complementary voltages on the pair of bit lines or the driving of the bit lines with complementary data. Thus, when a high state is applied to a word line (e.g., word line 44), access transistors 28 and 32 are rendered conductive. If bit lines 36 and 38 are then driven in a complementary fashion, the memory cell is forced to the state represented on bit lines 36 and 38, notwithstanding its prior memory state. Such a driving method is proven and well accepted, however, the differential driving and sensing techniques require an extra pair of bit lines as well as an extra pair of access transistors, all of which use up valuable semiconductor real estate.
In FIG. 3, a circuit is shown which employs single-ended bit-line writing/reading. Common components and levels to those shown in FIG. 2 are designated by identical numbers or letters. While the cell structure is simplified from that of FIG. 2, it presents operational problems when an attempt is made to switch the cell from the zero state to the one state. Assume that node X is at approximately ground potential due to the conduction of n-channel transistor 24 and the nonconduction of p-channel transistor 20. The low (ground) level at node X causes n-channel transistor 26 to be nonconductive and p-channel transistor 22 to be conductive. As a result, node Y is high (e.g. VDD).
If it is desired to drive node X to the one or high state, the potential on word line 44 is raised and causes access transistor 28 to become conductive. Bit line 36 is likewise raised to the high state (VDD). It is, however, difficult to raise the potential at node X to flip the cell. This is because the concurrent conduction of transistors 28 and 24 results in a voltage divider arrangement, and causes the voltage at node X to be at a potential between VDD and ground. Thus, while the node X potential rises as a result of the conduction of access transistor 28, it does not go sufficiently high to assure that the gate of transistor 26 is driven far enough positive to cause transistor 26 to go into heavy conduction. As a result, the cell may not flip under such conditions.
Similarly, to write a zero at node X (assuming it is already at the one or high state), word line 44 is driven high to VDD and bit line 36 is driven low to ground. It is however, difficult to lower the voltage at node X below a threshold logic level.
This is because when the left side of the cell exhibits the one state, transistor 24 is nonconductive and transistor 20 is conductive. Thus, notwithstanding the fact that bit line 36 drops to the low level, the potential at node X drops to a level determined by the voltage divider comprising transistors 20 and 28. The level at node X may therefore not drop below a logic threshold level that is required to assure the flipping of the cell.
It has been proposed that the operation of the cell in FIG. 3 could be improved by raising the word line "high" above VDD, using dynamic voltage boosting techniques. This solution is neither desirable nor practical because increased voltages across MOSFET's can degrade device reliability.
Other SRAM circuits and methods of operation can be found in the following prior art. In U.S. Pat. No. 4,660,177, to O'Connor, entitled "Dual Port Complementary Memory", a dual port memory cell is described which employs p and n access transistors to achieve cell simplification. That cell is also described in an article entitled "The Twin-Port Memory Cell", O'Connor, IEEE Journal of Solid States Circuits, Volume SC-22, No. 5, October 1987 pages 712-720. In addition, the O'Connor article considers a number of prior art SRAM circuits, including the circuit shown in FIG. 3 of this application.
U.S. Pat. No. 4,586,168 to Adlhoch et al., entitled "Dual Port Memory Sense Amplifier Isolation" describes a sense amplifier for a dual-port memory. The column select signal is deactivated as soon as the sense amplifier is set and read, enabling a faster write to the accessed cell. U.S. Pat. No. 4,541,076 to Bowers et al., entitled "Dual Port Random Access Memory", describes a system with CMOS dual-port memory operation. U.S. Pat. No. 4,580,245 to Ziegler et al., entitled "Complementary Metal Oxide Semiconductor Dual Port Random Access Memory Cell" describes a CMOS dual-port cell employing six transistors.
U.S. Pat. No. 4,618,945 to Sakurai et al., entitled "Semiconductor Memory Device" describes a memory system with master and local word lines. It also describes the concept of segmented word lines. U.S. Pat. No. 4,882,708 to Hayakawa et al., entitled "Semiconductor Memory Device", describes a memory with a "clear" mode wherein all of the word lines are selected simultaneously, resulting in a faster writing of identical data to all cells in the memory. U.S. Pat. No. 4,901,284 to Ochii et al., entitled "Static Random Access Memory" describes a SRAM cell with polysilicon loads and with means for detecting leaky cells.
U.S. Pat. No. 4,310,900 to Tsujide, entitled "Memory Device With Different Read and Write Power Levels" illustrates a prior art attempt at solving the problem above-described with respect to the circuit of FIG. 3. In specific, Tsujide describes a single-port memory cell with different read and write power levels. A single-port cell with four storage transistors and one access transistor is described wherein the write power supply level is lowered from the read power supply level. This action enables the voltage applied to the gate of the n-channel memory transistor that is conductive (storing a "O") to be lowered during the write cycle. As a result, the n-channel transistor is rendered marginally conductive, thereby enabling the potential at the input node (e.g. node X) to rise higher. However, because the circuit shown by Tsujide is a single port device, no consideration is given to the logic state on the complement side of the cell.
Accordingly, it is an object of this invention to provide an improved SRAM dual port memory cell having a small device count and occupying minimum silicon real estate.
It is another object of this invention to provide a six transistor, dual port SRAM cell wherein asynchronous access to and from both ports can occur.
It is another object of this invention to provide a six transistor, dual port SRAM cell wherein the transistors are not stressed through the use of over potentials.